Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “junction blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Conventionally, modules of a design instantiated in programmable logic of an FPGA (“FPGA fabric”) had very limited relocation possibilities. Heretofore, a module could only be instantiated in areas with equivalent logic layers and configuration memory layers. By equivalent logic layers for a columnar architected FPGA, it is meant an equivalent ordered set of stripes of columns of circuit resources, namely horizontally equivalent circuit resources. By equivalent configuration memory layers for a columnar architected FPGA, it is meant an equivalent mapping of resources to configuration memory, namely vertically equivalent configuration memory.
Accordingly, the mapping of configuration memory from one area of an FPGA to another area of the FPGA for identical logic layers and equivalent configuration memory layers may simply have involved offset addressing. Thus, having a portable module which could be instantiated in equivalent logic layer level areas of an FPGA meant the partial configuration bitstream (“partial bitstream”) associated with such module would have the same mapping for each of the different areas, except with some offset addressing. Thus, for example, if there were four areas on a FPGA designated for use of a module, then each of those four areas would have identical logic and configuration memory layers. Notably, as used herein, the term “configuration bitstream” generally refers to a bitstream that is used to completely instantiate a design in an FPGA. In contrast, the term “partial bitstream” generally refers to a bitstream that is used to instantiate only part of a design in an FPGA. A partial bitstream may be used to reconfigure a part of a design instantiated in an FPGA.
However, having to have identical logic and configuration memory layers for instantiation of a modular partial bitstream in different areas of an FPGA limits the possible locations for such instantiation. This limitation may be a constraint on the number of different types of modules that may be instantiated or may impose a greater commitment of FPGA fabric to accommodate such different types of modules than desirable, possibly resulting in having to purchase a larger, more expensive FPGA.
Accordingly, it would be desirable and useful to provide means to enhance the relocatability of partial bitstreams within an FPGA.